Hardware Systems Design

Learning Outcomes

The course aims to deepen the implementation of modern digital systems in silicon integrated circuits, covering topics related to physical design, clock timing and memory and data processing circuits.

Upon successful completion of the course, the student will possess the following knowledge, skills, and abilities: 

• Knowledge and understanding of Digital Circuit Design theory.
• Knowledge of practical industrial tools and FPGAs workflows.
  Understanding the proper process of describing a digital circuit in Verilog language so that it is composable by industrial tools.
• You will have applied your course knowledge and understanding of the process to complete the 4 Lab Assignments, implementing a variety of practical electronic circuits in the lab, and verifying their correct operation. For the successful implementation of the tasks, an analysis of their specifications is required, a synthesis of the knowledge, i.e. of the basic implementation units, but also finally an evaluation of the best synthesis.
• He will be able to describe implemented circuits by authoring a Technical Report, which describes the process of design, verification, testing and final implementation of the circuit.

Indicative Module Content

i. Review of Basic Digital Design Concepts

• Binary Numbers, Digital Logic, Electrical Circuit Characteristics
• Binary Algebra, Combinational and Sequential Gates
• Flip-Flop and Latch, and Conditions of Proper Operation
• Finite State Machines
• Types of Circuits

ii. Standard Flow of Electronic Design Automation

• Basic Electronic Design Automation Flow Stages
• Hierarchical Design
• Levels of Abstraction in Design – Material Description Languages

iii. The Verilog Hardware Description Language

• Language Features, Representation, and Implementation in Verilog
• Units, Appearances, Syntax, Time in Verilog
• Fundamentals, Modeling Types, Language Conventions
• Number Representation, Operators, Variable Types
• Assignments, Ports and Connections, Buses
• If/else conditions, case, Composability, Functional Control
• Sensitivity Lists, Initial/always Sections, Signal Concatenation
• for/while loops, Parameters, Memories, Functions, Procedures
• Events, Delays, Parallel Section Dependencies
• Composite Structures and Circuit Illustration
• Flip-Flops, Counters, Accumulator, Sliders, Multiplexers
• Encoders, Decoders, Adders, Comparators
• Edge Detector, D Latch, Synchronous/Asynchronous Memory
• Description of Finite State Machines in Verilog

iv. Numerical Circuits

• Half Adder and Full Adder, Serial Carry Adder
• Carry Forecast Aggregator, Carry Production and Promotion
• Multiplication Algorithm, Shift-Add Multiplier
• Multiplier with Table of Results, Multiplier of some Factors
• Algorithm of Division, Comparison, Shift and Subtraction

v. Synchronization and Metastasis

• Synchronization Cases, Transfer Curve and Mechanical Analog
• Synchronization with Flip-Flops, Metastasis, Synchronizer of two Flip-Flops
• Probability of Metastasis, Mean Time Between Failures
• Synchronization with Handshake Protocol and Queue

vi. Finite State Machines

• Definition of Finite State Machine, Flow Chart, State Graph
• Mealy/Moore Machines, Coding, Implementation of Finite State Machines in Binary Logic
• Initialization, Determinism, Indifference Values
• Interactive Finite State Machines, Composition of Multiple Finite State Machines
• Equivalent States, K-discrimination, K-equivalence
• Minimization of Fully-Definite Finite State Machines, Minimization with Indifference Values

vii. Binary Algebra, Binary Optimization

• Mapping Functions in Multidimensional Binary Space
• Boolean/Shannon Theorem, Normal Forms, Minimizers/Maximums
• Unanimity, Induction, SAT Problem, Indifference Values SDC/ODC
• Tautology, Inductive and First Inductive Terms
• Essential Inducers, Quine/McCluskey Theorem
• Calculating Primes with the Table method, One-Signal Problem Coverage
• Indifference Prices, Multiple Cost Functions

viii. Timing, Static Timing Analysis

• Combinatorial Delay, Sequential Gate, Intent/Hold Limits
• Modern Circuit Model – Path Types, Static Analysis
• Minimum Period, Conservation Violations, Designing Clock Trees
• Clock blocking